| POSITION |
Sr. ASIC Verification Engineer |
| JOB DESCRIPTION |
Experienced ASIC verification engineer that can take ownership of verification environment, develop new verification IP components in system verilog. Responsibilities include, developing of verification plan, verification IP module specs, writing system
verilog test benches and verification models, and debugging RTL designs. Candidate must enjoy being part of a dynamic start-up environment, that is highly motivated and customer focused to deliver high quality ASIC designs in a timely manner. |
EXPERIENCE/
QUALIFICATIONS |
BE (EEE, ECE, CSE) 5+ years experience
• Expert knowledge of System Verilog
• Experience writing test verification plans, and executing verification
components development to achieve coverage and schedule identified in
verification plan.
• Expertise with Mentor Questa systemVerilog simulation, and Novas Verdi
debugging environment.
• Must have led the verification, at least 2 complex multi million gate
ASICs
• Excellent communication skills. Organizational skill must include
effective Project tracking and reporting. |
JOB LOCATION/
WHERE TO APPLY |
Altierre Corporation, 1980 Concourse drive
San Jose, CA 95131 |
